1. Field of the Invention
The present invention relates generally to the field of microcontrollers (or microcomputers) and, more particularly, to power-saving mode release error detection and recovery logic circuits that permit microcomputers to recover their normal operation modes from a power-saving mode.
2. Related Art of the Invention
In the field of microcontrollers, power saving modes, such as, xe2x80x9cStopxe2x80x9d and xe2x80x9cIdlexe2x80x9d modes have been implemented to reduce power consumption of the microcontrollers during dormant periods. Such power saving modes are very useful in battery-powered small instruments incorporating microcontrollers, for example, remote control transmitters and smart cards.
Particularly, during stop mode, an on-chip primary oscillator of a microcontroller ceases generation of the microcontroller primary clock, so as to halt operation of its central processing unit (CPU) and all peripherals. In this manner, during stop mode, all system functions of a microcontroller are halted while the data stored in internal register files are retained, thereby reducing current consumption by the microcontroller. Once a microcontroller has entered stop mode, the microcontroller is held dormant in a wait status until the microcontroller is stimulated externally to reinitiate processing.
To cause the microcontroller to enter stop mode, a control register of the microcontroller may have to be loaded with a specific value before execution of a stop instruction. Stop mode is commonly released either by a system reset or by an external interrupt.
In the case of a microcontroller employing external interrupts to initiate release from stop mode, there is a need for certain bit settings in pertinent control registers such as interrupt control registers, input/output port mode control registers and a stop mode control register. If, however, the bits are not set correctly, owing to system noise, anomalies, or the like, then interrupt requests will not be serviced, and the microcontroller will not be released from stop mode. While system reset may be effective for releasing the device from stop mode, such system-wide resetting of registers is undesirable, as most information is lost upon system-wide reset.
Based upon the above, it can be appreciated that there presently exists a need for a microcontroller architecture that mitigates or eliminates the above-described limitations.
The present invention is accordingly directed to a microcontroller and method that substantially obviate the aforementioned limitations.
According to the present invention, a microcontroller with a power saving mode comprises a logic circuit that detects a power-save mode release command. The microcontroller exits power-save mode and recovers normal operation irrespective of the occurrence of errors due to erroneous programming of bit settings of interrupt control circuits and registers within the microcontroller.
According to a preferred aspect of the invention, a microcontroller includes a power-save release detection circuit which is connected to at least one data port sensing circuit, detects a transition in the level of the at least one data signal during operation in power-saving mode and releases the microcontroller from the power saving mode when the transition occurs.
The microcontroller may further comprise an interrupt control circuit and a logic gate circuit. The interrupt control circuit generates an interrupt processing control signal when at least one interrupt is generated by at least one interrupt source. The logic gate circuit has a first input for receiving a power-save release signal from the power-save release detection circuit, a second input for receiving an internal or external system reset signal to reset a system on which the microcontroller is mounted, a third input for receiving the interrupt processing control signal, and an output for providing an oscillation start signal to release the microcontroller from the power saving mode when at least one of the power-save release signal, the system reset signal and the interrupt processing control signal is activated. The data port sensing circuit preferably senses transitions in the level of input data at an input data port and output data at an output data port.
According to another preferred aspect of the invention, a microcontroller includes a clock generator, at least one input/output port circuit for inputting/outputting at least one data signal, and a power-save release detection circuit. The clock generator provides a microcontroller system clock signal in normal operation modes and test modes of the microcontroller. In the power saving mode of the microcontroller, the clock generator stops generating the microcontroller system clock signal. The power-save release detection circuit is connected to the at least one input/output port circuit. The power-save release detection circuit detects a level transition of the at least one input/output data signal in the power saving mode and generates a power-save release signal to release the clock generator from the power saving mode when the level transition of the at least one input/output data signal occurs, so that the clock generator resumes generating the microcontroller system clock signal in response to the power-save release signal.
According still another aspect of the invention, there is provided a method for resuming operation of a microcontroller having a power saving mode to reduce the power consumption of the microcontroller. In the method, the microcontroller is made to enter a power saving mode. A level transition of at least one input/output data signal at the microcomputer""s at least one data input/output terminal is detected in the power saving mode. When the level of the at least one input/output data signal transitions, the microcontroller is released from the power saving mode.